4.1.7 Register 6
7
6
5
4
3
2
1
0
AUTORESET PLL_INV
IRAM_OFF
FIFO_OFF
DIFF_OFF
MAP_OFF
AMPL
RES
AUTORESET Automatic Reset Setting
R/W 7
When this bit is 1, the L64777 loads the FIFO address
counters with the initial values in register 2 after the
detection of a FIFO alarm (pointer collision). When this
bit is 0, the FIFO address counters remain unchanged
after a pointer collision until an external microcontroller
intervenes. The reset value is 1.
PLL_INV
Phase Detector Setting
R/W 6
When this bit is 1, the L64777 exchanges the reference
and feedback inputs of the frequency and phase detector.
When this bit is 0, no exchange takes place. The reset
value is 0.
IRAM_OFF
Interleaver RAM Off
R/W 5
When this bit is 1, the L64777 switches the interleaver
RAM off after reset and initializes the RAM with 0 values
(not with the incoming data stream). The interleaver RAM
resumes normal operation as soon as the first sequence
start from the SSTARTIN pin (pin 90) comes in the data
stream. This setting is useful for getting a well-defined
chip output sequence. When this bit is 0, the L64777
uses the interleaver RAM in DVB-compliant mode on the
input data stream. The reset value is 1.
FIFO_OFF
FIFO Off
R/W 4
When this bit is 1, the L64777 switches the FIFO input
stage off and clocks the input data stream through three
internal registers from the ICLK to the OCLK domain.
When this bit is 0, the L64777 uses normal FIFO
processing and delay. The reset value is 0.
Note:
This mode requires ICLK to be exactly the same signal as
OCLK. You must connect these pins to each other.
DIFF_OFF
Differential Encoding Off
R/W 3
When this bit is 1, the L64777 switches the differential
encoding off. When this bit is 0, the L64777 encodes
according to the DVB standard. The reset value is 0.
Group 2 General-Purpose Registers
4-7
ETC [ ETC ]
