FIFO_INT
FIFO Interrupt
R/W 0
This bit enables generation of an interrupt in response to
a FIFO alarm. The reset value is 0.
4.2.4 Register 15
7
0
TEST
TEST
Reserved Test
R/W [7:0]
This register is reserved for LSI Logic production testing;
each bit field must be set to zero. The reset value is 0.
4.2.5 Registers 16, 17, and 18
23
0
INIT_STEP
INIT_STEP
R/W [23:0]
This value is the initial NCO step parameter. It is loaded
into the NCO when the most significant portion is written.
These are NCO-related register fields; they are used only
in PLL Mode. Bits 8 and 23 are reset to 0; all other bits
are reset to 1.
4.2.6 Registers 19 and 20
15
0
NCO_GAIN
NCO_GAIN
NCO Loop Bandwidth Adjustment
R/W [15:0]
The L64777 can use this parameter to adjust the NCO
loop bandwidth. The value becomes valid on writing to
the most significant portion. These are NCO-related
register fields; they are used only in PLL Mode 2. Bit 8 is
reset to 1; all other bits are reset to 0.
NCO-Related Registers
4-13
ETC [ ETC ]
