4.1.10 Register 11
7
6
5
4
0
UNCONST.
INPUT
TRACKSTEPS
GAP
TRACKSTEPS
Steps to Sync
R/W [7:6]
This value indicates the number of steps to acquire
synchronization and to declare loss of sync if the sync
pattern is missing for this number of events:
0b00 = 3
0b01 = 4
0b11 = 5
The reset value is 0b00.
UNCONST. INPUT
Unconstrained Input
R/W 5
The default setting of this bit is 0, which indicates that a
frame structure with a sync byte is required after every
(block length −1) bytes. If this bit is 1, any data stream is
accepted. The reset value is 0.
GAP
RS Code Bytes
R/W [4:0]
This is the number of bytes to be inserted for the RS
code at each end of a sync block. If the value is 0, there
is no modification of the incoming data stream. The
maximum value is 31 bytes to insert. This control
generates the gaps in the incoming stream for RS code
insertion. At the end of each block, readout of the FIFO
stops for the specified number of bytes. This determines
the value of FDEL (Register 2). The gap parameter
determines the number of bytes inserted into the symbol
stream, but not read from the FIFO. These bytes come
from the RS encoder; thus, the setting must be 16 (or 18
for the proprietary mode). The reset value is 0b10000.
Group 2 General-Purpose Registers
4-9
ETC [ ETC ]
