Note that the virtual FIFO, which indicates the FIFO under- or over-run,
is an internal location.
If the NCO_GAIN has reached the smallest possible value of 1, the
AUTO_ACQUISITION terminates. The AUTO_ACQUI_RUNNING bit
(Register 13, bit 3) sets to zero, indicating termination. If enabled, the
NCO can issue an interrupt on this condition.
This procedure updates the NCO step until the contents of the virtual
FIFO is zero during the measurement duration.
If ENABLE_NCO_LOOP and AUTO_ACQUI are not set, it is also
possible to set all parameters of the NCO loop through the
microprocessor interface and to run a frequency acquisition fully
controlled by the microprocessor. For monitoring purposes, it is possible
to read the current step and NCO_GAIN using the microprocessor
interface.
2.12.4 Regulation Phase
When the ENABLE_PHASE_LOOP bit is set in the NCO control register
(Register 14, bit 1), the loop starts running a phase compare between
the divided reference and the divided feedback clock. The NCO must set
counters CNT_I and CNT_O according to the rules applied for the other
PLL modes in Registers 7 through 10. The phase loop has a relatively
small gain, which can be adjusted in address 42. The NCO achieves a
phase lock only if the initial frequency is already close to the desired
range.
2.13 Interpolator
In PLL Mode 2, the interpolator retimes the output samples that the
Nyquist filter calculated. The interpolator is clocked with PCLK and
generates the output samples in the PCLK sampling grid. The
interpolator takes the required retiming information from the NCO.
PCLK is at least twice the frequency of the original OCLK obtained by
the formula for PLL Mode 1. The square-root raised cosine filter also
compensates for the sin(x)/x frequency characteristic of the digital-to-
analog converter with the faster sampling grid.
Interpolator
2-39
ETC [ ETC ]
