Attention: The internal microprocessor registers are not double-
buffered, and they influence the processing modes of the
L64777 asynchronously during operation. Thus, all mode
changes place the chip in an undefined state until an
SSTARTIN pulse synchronously resets the sequences of
the data path. When a FIRSTOUT pulse grants the
sequence reset at the output, the chip becomes fully
operational again. The normal chip initialization procedure
is as follows:
–
–
–
Reset after power-up.
Initialize ALL microprocessor registers.
Apply a negative slope of SSTARTIN to reset all
sequences at the beginning of the next sync block.
–
Apply a negative slope of SSTARTIN after all mode
changes from the microprocessor interface and wait for
FIRSTOUT.
Also, the serial interface requires a clock for internal operation, either
through the OCLK input or from the internal VCO to program the device.
Furthermore, there is a lower limit for this clock: its frequency must be at
least eight times that of SCL.
2.15 Test Unit
The L64777 supports:
•
•
•
•
•
Full scan test
BIST for the two RAMs
JTAG boundary scan
Digital-to-analog conversion test
PLL tests
Select the L64777 test modes through the FTMODE pins. The default
values for normal operation are:
FTMODE = 000, SCAN_ENABLE = 0, TNn = 1.
If TNn is cleared, all outputs are high-impedance.
Test Unit
2-41
ETC [ ETC ]
