The global control manages the output data stream so that it is
continuous (no gaps between the symbols), assuming that the incoming
data rate is constant (on average). To achieve this, a PLL must derive
the output clock OCLK from the input transport stream rate.
The PLL module consists of two independent clock dividers for ICLK and
OCLK. The dividers are 15-bit binary counters that have a count
sequence length that is programmable through Registers 7 through 10.
The default values written by the external microprocessor are: OCLK
divider = 32, ICLK divider = 6 for 64 QAM.
2.12.1 Numerically Controlled Oscillator (NCO)
In PLL Mode 2, an NCO generates the internal clocking (OCLK, SCLK)
and the control information for the interpolator. The NCO is locked to
ICLK clock and operates with the processing clock PCLK provided from
L64724. PCLK must be at least twice as fast as the necessary OCLK.
To lock the loop with low jitter, program the NCO with a frequency close
to the ideal value obtained from the formulae given for the other PLL
modes. A phase loop in a second step does the fine regulation (see
Figure 2.22).
To find the required initial frequency, the device supports two modes: a
frequency measurement unit, and an automated frequency acquisition.
These are described in the following sections.
Global Control and PLL Module
2-35
ETC [ ETC ]
