6. The master then sends the 8-bit data, which initializes the base
pointer (APR0/1).
7. The master repeats the start condition.
8. The master transmits the 7-bit slave address.
9. The master sets the R/W bit = 0 to indicate a write cycle.
10. The addressed slave acknowledges the reception by driving SDA
LOW in the ACK cycle.
11. The master transmits the number of the group that it wishes to read,
which the slave acknowledges.
12. The master issues another start condition.
13. The master transmits the 7-bit slave address.
14. The master sets the R/W bit = 1 to indicate a read cycle.
15. The slave drives SDA LOW to acknowledge.
16. The slave starts transmitting the data, MSB first.
17. The master has to provide the acknowledge by driving SDA LOW
during the ACK cycle.
18. In the case of a single read, the master does not drive SDA LOW
during the ACK cycle after reception of the first byte. The slave
responds to this by relinquishing control of the bus and waiting for
the master to issue a stop condition. For burst reads, the master
drives SDA LOW for each byte it receives during the ACK cycle,
except for the last byte.
19. The master terminates the cycle by issuing a stop condition.
A-6
Programming the L64777 in Serial Host Interface Mode
ETC [ ETC ]
