Figure A.2 Serial Bus Write/Read Cycle
Start
Stop
Condition
Condition
SCL
Write Cycle
bit1 R/W bit7
bit7
bit7
bit7
bit6
bit5
bit4
bit3
bit2
bit6
bit5
bit4
bit3
bit2
bit1 bit0
SDA
SDA
SDA
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Transmitter, Slave-Receiver
(Master transmits data to slave)
ACK Cycle: Slave
Read Cycle (burst)
bit6
bit5
bit4
bit3
bit2
bit1
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0
bit7
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Receiver, Slave-Transmitter
(Slave transmits data to master)
ACK Cycle: Master
Single-Read Cycle
bit6
bit5
bit4
bit3
bit2
bit1
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
ACK Cycle: Slave
Master-Receiver, Slave-Transmitter
(Slave transmits data to master)
ACK Cycle: Master
Stop
Condition
Start Condition: The master (which drives the SCL) indicates the start of a cycle by pulling SDA to LOW when
SCL is HIGH.
Stop Condition: The master (which drives the SCL) indicates the end of a cycle by releasing SDA to HIGH when
SCL is HIGH.
Data Transfer: All data changes on the SDA line happen only when clock is LOW, except for the special cases
outlined above to indicate cycle Start/Stop.
Acknowledge: The receiver always generates the acknowledge. In the case of a single read, the master-receiver
does not generate an ACK so that it can generate the Stop condition (as indicated above).
Serial Bus Protocol Overview
A-3
ETC [ ETC ]
