CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Functional Block Diagram—128Kx36[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
BWd#
D
Q
Q
CE#
CE2
ENABLE
D
D
Q
CE2#
OE#
ZZ
Power Down Logic
Input
Register
ADSP#
15
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQa,DQb
DQc,DQd
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Functional Block Diagram—256Kx18[1]
BYTE b
WRITE
BWb#
BWE#
D
Q
BYTE a
WRITE
BWa#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
16
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQa,DQb
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2
ETC [ ETC ]
