Register Description
3.4.9
HDR1—Header Type Register (Device 1)
Offset:
Default:
Access:
Size:
0Eh
01h
Read Only
8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Descriptions
7:0
Header Type (HEADT). This read only field always returns 01h when read. Writes have no effect.
3.4.10
PBUSN—Primary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
18h
00h
Read Only
8 bits
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus #0.
Bit
Descriptions
7:0
Bus Number. Hardwired to “0”.
3.4.11
SBUSN—Secondary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
19h
00h
Read /Write
8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI
bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to AGP.
Bit
Descriptions
Bus Number. Programmable
7:0
Default “0”.
82443BX Host Bridge Datasheet
3-53
ETC [ ETC ]
