Register Description
3.4.4
PCISTS1—PCI-to-PCI Status Register (Device 1)
Address Offset:
Default Value:
Access:
06–07h
0220h
Read Only, Read/Write Clear
16 bits
Size:
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the “virtual” PCI-to-PCI bridge embedded within the 82443BX.
Bit
Descriptions
15
14
13
12
11
10:9
8
Detected Parity Error (DPE1). Not Applicable. Hardwired to 0.
Reserved.
Received Master Abort Status (RMAS1). Not Applicable. Hardwired to 0.
Received Target Abort Status (RTAS1). Not Applicable. Hardwired to 0.
Signaled Target Abort Status (STAS1). Not Applicable. Hardwired to 0.
DEVSEL# Timing (DEVT1). Not Applicable. Hardwired to “01b”.
Data Parity Detected (DPD1). Not Applicable. Hardwired to 0.
Fast Back-to-Back (FB2B1). Not Applicable. Hardwired to 0.
Reserved.
7
6
5
66/60 MHz Capability. Hardwired to “1”.
4:0
Reserved.
3.4.5
RID1—Revision Identification Register (Device 1)
Address Offset:
Default Value:
Access:
08h
00/01h
Read Only
8 bits
Size:
This register contains the revision number of the 82443BX device #1. These bits are read only and
writes to this register have no effect. For the A-0 Stepping, this value is 00h.
Bit
Description
Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for the 82443BX device #1.
7:0
02h = B1 stepping
82443BX Host Bridge Datasheet
3-51
ETC [ ETC ]
