Register Description
3.3.41
BUFFC—Buffer Control Register (Device 0)
Offset:
Default:
Access:
Size:
F0–F1h
0000h
Read/Write
16 bits
The Jam Latch design provides the AGP sub-system with a variable strength, to better
accommodate the clamping requirements.
The Jam Latch Register should be enabled by the BIOS during the resume sequence from STR, if
these Jam Latch control bits had been enabled before the STR was executed.
Bit
Description
15:10
Reserved.
AGP Jam Latch Strength Select.
Bit 9 = 1; Enable strong pull-up
Bit 8 = 1; Enable weak pull-up
Bit 7 = 1; Enable strong pull-down
Bit 6 = 1; Enable weak pull-down
9:6
5:0
Intel Reserved.
82443BX Host Bridge Datasheet
3-47
ETC [ ETC ]
