Functional Description
4.8.2.1
CPU Reset
The CPU reset is generated by the 82443BX in the following case:
• CPURST# is always asserted if PCIRST# is asserted.
• CPURST# is asserted during resume sequence from POS CRst_En= 1.
The 82443BX deasserts CPURST# 1 ms after detecting the rising edge of PCIRST#. The
CPURST# is synchronous to host bus clock.
Figure 4-7. Reset CPURST# in a Desktop or Mobile System When PCIRST# Asserted
HCLK
PCIRST#
1m SEC
0
0
0
0
1
2
PCLK
CPURST#
CRESET#
....
PCIRST# must be asserted when the system resumes from low power mode of which power is
removed, including resume from STR or STD and power up sequence. In these cases, CPURST# is
activated with the assumption that CPU power is removed as well and in order to enforce correct
resume sequence.
When resuming from POS, the PCIRST# and CPURST# are typically not used, to speed up the
resume sequence. The option to reset the CPU, in this case, is available by using the CRst_En
configuration bit option.
When the user performs a soft reset, the PIIX4E drives SUSTAT# to the 82443BX. This forces the
82443BX to switch to a suspend refresh state. When the BIOS attempts to execute cycles to
DRAM, the 82443BX will not accept these cycles because it believes that it is in a suspend state.
After coming out of reset, software must set the Normal refresh enable bit (bit4, Power
Management Control register at Offset 7Ah) in the 82443BX before doing an access to memory.
4.8.2.2
CPU Clock Ratio Straps
The Pentium Pro processors require their internal clock ratio to be set up via strapping pins
multiplexed onto signals A20M#, IGNE#, INTR, and NMI. These signals should reflect the
strapping values during the deasserted edge of CPURST# signal and be held stable for between 2 to
20 clocks. HCLKs after CPURST# is deasserted.
The 82443BX is designed to support CPU strapping options with external logic, when PIIX4E is
used. Figure 4-8 illustrates the strapping pin timing when using the external glue logic (necessary
for PIIX4E). The external mux is switched via the CRESET# signal which is a 2 clock delayed
version of CPURST#.
82443BX Host Bridge Datasheet
4-33
ETC [ ETC ]
