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FW82443BX 参数 Datasheet PDF下载

FW82443BX图片预览
型号: FW82443BX
PDF下载: 下载PDF文件 查看货源
内容描述: 控制器杂项 - 数据表参考\n [Controller Miscellaneous - Datasheet Reference ]
分类和应用: 控制器
文件页数/大小: 132 页 / 642 K
品牌: ETC [ ETC ]
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Functional Description  
SDRAM Suspend Refresh  
When the 82443BX is configured for 3 DIMMs, six CKE signals are provided. When the 82443BX  
is configured for 4 DIMMs, a single GCKE (global CKE) is provided to allow an external device to  
correctly drive the external CKE signals to the SDRAM devices. An additional 3 DIMM  
configuration is where only CKE0 is provided. A detailed description of the DRAM signal  
functions is given in the Chapter 2, “Signal Description”.  
For the Registered DIMMs the CKE function is not supported. The stacking technology used for  
registered DIMMs prohibits the use of the CKE function. For registered DIMMs, components are  
stacked on top of one another. The stacked components are physically in the same row, but  
logically in separate rows. The stacked components connect all pins together, except for the CS#  
pin, in order to address components in different rows. Since the CKE pins for the components are  
connected together, and the components are logically in different rows, the CKE function is not  
supported.  
Table 4-18. SDRAM Suspend Refresh Configuration Modes  
MM  
CONFIG  
SDRAM  
PWR  
FUNCTION  
3 DIMM, CKE[5:0] driven, self-refresh entry staggered. SDRAM dynamic  
power down available.  
0
1
0
0
X
1
3 DIMM, CKE0 only, self-refresh entry not staggered. SDRAM dynamic power  
down unavailable.  
4 DIMM, GCKE only, self-refresh entry staggered. SDRAM dynamic power  
down unavailable.  
EDO DRAM Suspend Refresh  
The 82443BX NB supports two modes of EDO refresh during suspend: CAS-before-RAS and Self-  
refresh. The refresh mode is dependent on the Suspend Refresh type bit (SRT) in the Miscellaneous  
Control Register.  
4.8.4  
Clock Control Functions  
The 82443BX implements an independent Clock Gating power savings feature to reduce its own  
average power consumption. The 82443BX clock gating functions works along with the primary  
PCI bus CLKRUN# function.  
The Clock Gating function is enabled by setting the GCLKEN Configuration bit. This function  
default value is 0. The AGP interface’s clock domain can be permanently disabled by the AGP_DIS  
configuration bit. This allows further power savings in systems that AGP is not used.  
CLKRUN Clocking States  
There are three states in the CLKRUN# protocol:  
Clock Running: The clock is running and the bus is operational.  
Clock Stop Request: The central resource has indicated on the CLKRUN# line that  
the clock is about to stop.  
Clock Stopped: The clock is stopped with CLKRUN# being monitored for a restart.  
82443BX Host Bridge Datasheet  
4-35  
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