Functional Description
Table 4-14. Low Power Mode
82443BX
State
POS Exit
PCIRST
External Clk
HCLK PCLK
System Suspend State
Description
HCLK
PCLK
The 82443BX is fully on and
operating normally.
Powered-On
ON
ON
N/A
N/A
Active
Active
Active
Internal clock gating as well as PCI
CLKRUN# may be enabled.
This is transparent to the 82443BX
as external HCLK and PCLK are
unaffected. Host Bus is Idle however.
CPU STOP_GRANT /
QUICK_START
Active
(C2)
Internal clock gating as well as PCI
CLKRUN# may be enabled.
HCLK clock is kept low. The
82443BX maintains DRAM refresh
using suspend refresh.
CPU STOP CLOCK (C3)
(DEEP SLEEP)
Low or
Active
POS
POS
N
N
Low
Low
The only running clock is the RTC
clock. The 82443BX maintains
DRAM refresh using suspend
refresh. When resume, the 82443BX
may or may not generate CPU reset.
Powered On Suspend
(POS, POSCL)
Low
Low
The only running clock is the RTC
clock. The 82443BX maintains
DRAM refresh using suspend
refresh. On resume, PIIX4E
generates PCI reset.
Powered On Suspend
(POSCL)
Y
Low
CPU and other components (with the
exception of DRAM and PIIX4E
resume logic) are assumed to be
powered OFF.
Suspend to RAM
(STR)
POS
OFF
Y
Low
Low
The 82443BX maintains DRAM
refresh using suspend refresh. All
82443BX logic, with the exception of
resume and refresh are inactive.
Entire system is powered OFF except
for PIIX4E resume and RTC wells.
Upon resume, the 82443BX resets its
entire state.
Suspend -to-Disk (STD)
or Powered-Off
N/A
X
X
82443BX Host Bridge Datasheet
4-31
ETC [ ETC ]
