R
XC5200 Series Field Programmable Gate Arrays
VersaRing Input/Output Interface
XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP can also support two USERCODE
instructions. When the boundary scan configuration option
is selected, three normal user I/O pins become dedicated
inputs for these functions. Another user output pin
becomes the dedicated boundary scan output.
The VersaRing, shown in Figure 18, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The Ver-
saRing decouples the core logic from the I/O pads. Each
VersaRing Cell provides up to four pad-cell connections on
one side, and connects directly to the CLB ports on the
other side.
Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
after configuration provides flexibility for interconnect test-
ing.
VersaRing
2
8
8
8
2
2
Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused out-
puts in IOBs used as unidirectional input pins. This tech-
nique partially compensates for the lack of INTEST
support.
Pad
Pad
Pad
Pad
2
GRM
10
Interconnect
4
The user can serially load commands and data into these
devices to control the driving of their outputs and to exam-
ine their inputs. This method is an improvement over
bed-of-nails testing. It avoids the need to over-drive device
outputs, and it reduces the user interface to four pins. An
optional fifth pin, a reset for the control logic, is described in
the standard but is not implemented in Xilinx devices.
4
VersaBlock
8
8
Interconnect
8
2
Pad
Pad
Pad
Pad
2
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction regis-
ter and a number of data registers. The functional details
can be found in the IEEE 1149.1 specification and are also
discussed in the Xilinx application note XAPP 017: “Bound-
ary Scan in XC4000 and XC5200 Series devices”
GRM
10
4
4
VersaBlock
2
Figure 19 on page 99 is a diagram of the XC5200-Series
boundary scan logic. It includes three bits of Data Register
per IOB, the IEEE 1149.1 Test Access Port controller, and
the Instruction Register with decodes.
8
2
X5705
Figure 18: VersaRing I/O Interface
The public boundary-scan instructions are always available
prior to configuration. After configuration, the public instruc-
tions and any USERCODE instructions are only available if
specified in the design. While SAMPLE and BYPASS are
available during configuration, it is recommended that
boundary-scan operations not be performed during this
transitory period.
Boundary Scan
The “bed of nails” has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti-
cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE boundary scan standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan-compatible IC. IEEE 1149.1-compatible
devices may be serial daisy-chained together, connected in
parallel, or a combination of the two.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the FPGA
device, and to read back the configuration data.
All of the XC4000 boundary-scan modes are supported in
the XC5200 family. Three additional outputs for the User-
Register are provided (Reset, Update, and Shift), repre-
7-98
November 5, 1998 (Version 5.2)
ETC [ ETC ]
