R
XC5200 Series Field Programmable Gate Arrays
Matrix through a hierarchy of different-length metal seg-
ments in both the horizontal and vertical directions. A pro-
GRM
GRM
GRM
GRM
GRM
GRM
GRM
Versa-
Block
Versa-
Block
Versa-
Block
1
GRM
Versa-
Block
Versa-
Block
Versa-
Block
2
GRM
Versa-
Block
Versa-
Block
Versa-
Block
3
4
7
Six Levels of Routing Hierarchy
GRM
4
4
1
2
Single-length Lines
24
24
TS
Double-length Lines
CLB
LC3
LC2
LC1
LC0
4
3
Direct Connects
4
4
4
4
4
5
Longlines and Global Lines
Local Interconnect Matrix
6
LIM
LIM
5
Logic Cell Feedthrough
Path (Contained within each
Logic Cell)
6
4
4
X4963
Direct Connects
Figure 15: XC5200 Interconnect Structure
grammable interconnect point (PIP) establishes an electri-
cal connection between two wire segments. The PIP, con-
sisting of a pass transistor switch controlled by a memory
element, provides bidirectional (in some cases, unidirec-
tional) connection between two adjoining wires. A collec-
tion of PIPs inside the General Routing Matrix and in the
Local Interconnect Matrix provides connectivity between
various types of metal segments. A hierarchy of PIPs and
associated routing segments combine to provide a power-
ful interconnect hierarchy:
•
•
•
Forty bidirectional single-length segments per CLB
provide ten routing channels to each of the four
neighboring CLBs in four directions.
Sixteen bidirectional double-length segments per CLB
provide four routing channels to each of four other
(non-neighboring) CLBs in four directions.
Eight horizontal and eight vertical bidirectional Longline
November 5, 1998 (Version 5.2)
7-95
ETC [ ETC ]
