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XC5202-5VQ100I 参数 Datasheet PDF下载

XC5202-5VQ100I图片预览
型号: XC5202-5VQ100I
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 73 页 / 583 K
品牌: ETC [ ETC ]
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R
XC5200 Series Field Programmable Gate Arrays  
To GRM  
M0-M23  
24  
8
TS  
4
Global Nets  
4
To  
C
OUT  
Longlines  
and GRM  
TQ0-TQ3  
4
4
4
4
4
North  
South  
East  
CLB  
5
5
5
5
3
LC3  
LC2  
LC1  
LC0  
Input  
Multiplexers  
Output  
Multiplexers  
West  
3
Direct to  
East  
V
CC  
/GND  
4
8
3
3
4
Direct North  
4
CLK  
CE  
Feedback  
4
CLR  
C
IN  
Direct West  
4
4
X5724  
Direct South  
Figure 14: VersaBlock Details  
CLB inputs have several possible sources: the 24 signals  
from the GRM, 16 direct connections from neighboring  
VersaBlocks, four signals from global, low-skew buffers,  
and the four signals from the CLB output multiplexers.  
Unlike the output multiplexers, the input multiplexers are  
not fully populated; i.e., only a subset of the available sig-  
nals can be connected to a given CLB input. The flexibility  
of LUT input swapping and LUT mapping compensates for  
this limitation. For example, if a 2-input NAND gate is  
required, it can be mapped into any of the four LUTs, and  
use any two of the four inputs to the LUT.  
The direct connects also provide a high-speed path from  
the edge CLBs to the VersaRing input/output buffers, and  
thus reduce pin-to-pin set-up time, clock-to-out, and combi-  
national propagation delay. Direct connects from the input  
buffers to the CLB DI pin (direct flip-flop input) are only  
available on the left and right edges of the device. CLB  
look-up table inputs and combinatorial/registered outputs  
have direct connects to input/output buffers on all four  
sides.  
The direct connects are ideal for developing customized  
RPM cells. Using direct connects improves the macro per-  
formance, and leaves the other routing channels intact for  
improved routing. Direct connects can also route through a  
CLB using one of the four cell-feedthrough paths.  
Direct Connects  
The unidirectional direct-connect segments are connected  
to the logic input/output pins through the CLB input and out-  
put multiplexer arrays, and thus bypass the general routing  
matrix altogether. These lines increase the routing channel  
utilization, while simultaneously reducing the delay  
incurred in speed-critical connections.  
General Routing Matrix  
The General Routing Matrix, shown in Figure 15, provides  
flexible bidirectional connections to the Local Interconnect  
7-94  
November 5, 1998 (Version 5.2)