R
XC5200 Series Field Programmable Gate Arrays
Typically, a 0.1 µF capacitor connected near the Vcc and
Ground pins of the package will provide adequate decou-
pling.
Optional
To User
Logic
IBUF
BSCAN
RESET
Output buffers capable of driving/sinking the specified 8 mA
loads under specified worst-case conditions may be capa-
ble of driving/sinking up to 10 times as much current under
best case conditions.
UPDATE
SHIFT
TDO
TDI
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default)
which should be used where output rise and fall times are
not speed-critical.
TMS
TCK
DRCK
IDLE
To User
Logic
TDO1
TDO2
SEL1
From
User Logic
SEL2
X9000
Figure 20: Boundary Scan Schematic Example
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep
TMS High, and then apply whatever signal is desired to TDI
and TCK.
GND
Ground and
Vcc Ring for
I/O Drivers
Avoiding Inadvertent Boundary Scan
Vcc
Vcc
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
Logic
Power Grid
7
GND
X5422
To prevent activation of boundary scan during configura-
tion, do either of the following:
Figure 21: XC5200-Series Power Distribution
•
TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or Low—do not toggle this clock input.
Pin Descriptions
There are three types of pins in the XC5200-Series
devices:
•
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017, “Boundary Scan in
XC4000 and XC5200 Devices.“
•
•
•
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Power Distribution
Before and during configuration, all outputs not used for the
configuration process are 3-stated and pulled high with a
20 kΩ - 100 kΩ pull-up resistor.
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 21. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
After configuration, if an IOB is unused it is configured as
an input with a 20 kΩ - 100 kΩ pull-up resistor.
Device pins for XC5200-Series devices are described in
Table 9. Pin functions during configuration for each of the
seven configuration modes are summarized in “Pin Func-
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
November 5, 1998 (Version 5.2)
7-101
ETC [ ETC ]
