VS1001K
VLSI
DATASHEET
y
Solution
6. SPI BUSES
6.5 SPI Timing Diagram
tWL tWH
tXCSH
tXCSS
XCS
tXCS
0
1
14
15
16
SCK
SI
tSU
tH
SO
tZ
tV
tDIS
Figure 9: SPI Timing Diagram.
Symbol Min Max Unit
tXCSS
tSU
tH
5
10
42
ns
ns
ns
tZ
42 ns
ns
ns
42 ns
ns
tWL
tWH
tV
tXCSH
tXCS
tDIS
100
100
10
2
XTALI cycles
XTALI cycles
1
Note: As tXCS must be at least 2 clock cycles, the maximum speed for the SPI bus is 1/4 of VS1001k’s
internal clock speed. For details, see Application Notes for VS10XX.
Version 4.11, 2003-09-18
19
ETC [ ETC ]
