VS1001K
VLSI
DATASHEET
y
Solution
6. SPI BUSES
6 SPI Buses
6.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1001k’s
Serial Data Interface SDI (Chapters 6.3 and 7.3) and Serial Control Interface SCI (Chapters 6.4 and 7.4).
6.2 SPI Bus Pin Descriptions
SDI Pin SCI Pin Description
-
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
DCLK
SCK
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written (clock 0 in the
following figures).
SDATA
-
SI
SO
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
6.3 Serial Protocol for Serial Data Interface (SDI)
The serial data interface can operate in either master or slave mode. In master mode, VS1001k generates
the DCLK signal, which can be selected to be either 512 or 1024 kHz. In slave mode, the DCLK signal
is generated by an external circuit.
The data (SDATA signal) can be clocked in at either the rising or falling edge of the DCLK. (Chapter 7.5).
The VS1001k chip assumes its input to be byte-sychronized. I.e. the internal operation of the decoder
does not search for byte synchronization of the frames from the data stream, but instead assumes the
data to be correctly byte-aligned. The bytes can be transmitted either MSB or LSB first, depending of
contents of SCI register MODE (Chapter 7.5).
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 6: BSYNC Signal.
To ensure correct byte-alignment of the input bitstream, the serial data interface has a BSYNC signal.
Version 4.11, 2003-09-18
16
ETC [ ETC ]
