VS1001K
VLSI
DATASHEET
y
Solution
6. SPI BUSES
The first DCLK sampling edge (rising or falling, depending on selected polarity), during which the
BSYNC is high, marks the first bit of a byte (LSB, if LSB-first order is used, MSB, if MSB-first order
is used). If BSYNC is not used, it must be tied to VCC externally and the master of the input serial
interface must always sustain the correct byte-alignment. Using BSYNC is strongly recommended. For
more details, look at the Application Notes for VS10XX.
The DREQ signal of the data interface is used in slave mode to signal if VS1001k’s FIFO is capable of
receiving more input data. If DREQ is high, VS1001k can take at least 32 bytes of data. When there is
less than 32 bytes of free space, DREQ is turned low, and the sender should stop transferring new data.
Because of the 32-byte safety area, the sender may send upto 32 bytes of data at a time without checking
the status of DREQ, making controlling VS1001k easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
6.4 Serial Protocol for Serial Command Interface (SCI)
6.4.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 7.4) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should not update data at the rising edge.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Instruction
Name
Opcode
Operation
READ
0000 0011 Read data
WRITE 0000 0010 Write data
Note: After using the Serial Command Interface, it is not allowed to send SCI or SDI data for 5 mi-
croseconds.
6.4.2 SCI Read
VS1001k registers are read by the following sequence. First, XCS line is pulled low to select the device.
Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit word address. After the
address has been read in, any further data on SI is ignored. The 16-bit data corresponding to the received
address will be shifted out onto the SO line.
XCS should be driven high after the data has been shifted out. In that case, the word address will be
incremented and data corresponding to the next address will be shifted out. After the last word has been
shifted out, XCS should be driven high to end the READ sequence.
Version 4.11, 2003-09-18
17
ETC [ ETC ]
