VS1001K
VLSI
DATASHEET
y
Solution
7. FUNCTIONAL DESCRIPTION
power is needed when activating this feature, see Application Notes for VS10XX.
ampl/dB
+3
+2
+1
0
−1
−2
−3
f/Hz
10
20
50
100
200
500
1k
2k
5k
10k
20k
Figure 11: Built-In Bass/Treble Enhancer Frequency Response at 44.1 kHz.
SM DACT defines the active edge of data clock for SDI.
SM BYTEORD defines the data order inside a byte for SDI. Bytes are, however, still sent in the default
order.
SM IBMODE sets input bus to master mode. Master mode has not been tested, and its use is not recom-
mended.
SM IBCLK sets the bus clock speed when VS1001k is the master.
Version 4.11, 2003-09-18
23
ETC [ ETC ]
