NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
t
WTR
BAa, COL n
BAa, COL b
Address
CL = 2
t
(max)
DQSS
DQS
DQ
DIa- b
1
1
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
t
WTR
BAa, COL b
BAa, COL n
Address
CL = 2
t
(min)
DQSS
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
is referenced from the first positive CK edge after the last data in pair.
t
WTR
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Don’ t Care
36
REV 1.0
May, 2001
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NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
ETC [ ETC ]
