CXD3018Q/R
Command bit
KSL1
Processing
VCOSEL2
0
KSL0
0
Wide-band PLL VCO2 is set to normal 1× speed, and the output is 1/1
0
0
1
1
0
0
1
1
frequency-divided.
Wide-band PLL VCO2 is set to normal 1× speed, and the output is 1/2
0
0
0
1
1
1
1
1
0
1
0
1
0
1
frequency-divided.
Wide-band PLL VCO2 is set to normal 1× speed, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to normal 1× speed, and the output is 1/8
frequency-divided.
Wide-band PLL VCO2 is set to approximately 2× speed, and the
output is 1/1 frequency-divided.
Wide-band PLL VCO2 is set to approximately 2× speed, and the
output is 1/2 frequency-divided.
Wide-band PLL VCO2 is set to approximately 2× speed, and the
output is 1/4 frequency-divided.
Wide-band PLL VCO2 is set to approximately 2× speed, and the
output is 1/8 frequency-divided.
Command bit
VCO2 THRU = 0
VCO2 THRU = 1
Processing
V16M output is internally connected to VCKI. Set VCKI to low.
V16M output is not internally connected. Input the clock from VCKI.
These bits select the internal or external connection for the VCO2 used in CAV-W mode.
Command bit
TXON = 0
Processing
When CD TEXT data is not demodulated, set TXON to 0.
When CD TEXT data is demodulated, set TXON to 1.
TXON = 1
See "§4-14. CD TEXT Data Demodulation"
– 37 –
ETC [ ETC ]
