CXD3018Q/R
Sync protection window width
Command bit
WSEL = 1
Application
1
±26 channel clock
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
1 In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Processing
VCOSEL1
0
KSL3
0
KSL2
0
Multiplier PLL VCO1 is set to 1× speed, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to 1× speed, and the output is 1/2
frequency-divided.
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Multiplier PLL VCO1 is set to 1× speed, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to 1× speed, and the output is 1/8
frequency-divided.
Multiplier PLL VCO1 is set to approximately 2× speed, and the output
is 1/1 frequency-divided.
Multiplier PLL VCO1 is set to approximately 2× speed, and the output
is 1/2 frequency-divided.
Multiplier PLL VCO1 is set to approximately 2× speed, and the output
is 1/4 frequency-divided.
Multiplier PLL VCO1 is set to approximately 2× speed, and the output
is 1/8 frequency-divided.
Command bit
Processing
VCO1CS0 = 0
VCO1CS0 = 1
Multiplier PLL VCO1 low speed is selected.
Multiplier PLL VCO1 high speed is selected.
The CXD3018Q/R has two VCO1s, and this command selects one of these VCO1s.
Block Diagram of VCO Internal Path
VCO1SEL1
1/1
Low-speed
VCO1
1/2
To DSP interior
1/4
High-speed
VCO1
1/8
VCO1CS0
KSL3, 2
VCO1 Internal Path
– 36 –
ETC [ ETC ]
