CXD3018Q/R
Command bit
DSSP512Fs
1
Processing
DSSP block master clock selection. Crystal = 512Fs (22.5792MHz)
DSSP block master clock selection. Crystal = 768Fs (33.8688MHz) or
Crystal = 384Fs (16.9344MHz)
0
See "§5-2. Digital Servo Block Master Clock (MCK)".
Processing
Command bit
LMUT and RMUT pins are high when muted.
ZDPL = 1
ZDPL = 0
LMUT and RMUT pins are low when muted.
See "Mute flag output" for the mute flag output conditions.
Processing
Command bit
ZMUT = 1
ZMUT = 0
Zero detection mute is on.
Zero detection mute is off.
Set ZDPL to 1 when zero detection mute is on.
Processing
Command bit
DCOF = 1
DCOF = 0
DC offset is off.
DC offset is on.
DCOF can be set when OPSL1 = 1.
Set DC offset to off when zero detection mute is on.
Processing
Command bit
DACPWDN = 1
DACPWDN = 0
Normal operation
The clock is stopped for the DAC block. This makes the power consumption reduced.
$AX commands (OPSL2 = 0)
Data 2 and subsequent data are for DF/DAC function settings.
Data 2
Data 3
D3 D2
Data 1
Command
D3
0
D2
0
D1
D0
D3
0
D2
D1
0
D0
Mute ATT
0
EMPH SMUT AD10
Audio CTRL
OPSL2
Data 3
Data 4
D2
D1
Data 6
Data 5
D2 D1
D1
D0
D3
D0
D3
D3
D2
D1
D0
D0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
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ETC [ ETC ]
