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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
$3D (preset: $3D 00 00)  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7  
0
D6  
0
D5  
0
D4  
0
D3  
0
D2  
0
D1  
0
D0  
0
SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0  
SFID:  
SFSK:  
THID:  
THSK:  
SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK  
filter second-stage output.  
When the low frequency component of the tracking error signal obtained from the RF amplifier  
is attenuated, the low frequency can be amplified and input to the SLD servo filter.  
Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the  
DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2,  
and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to  
M00 can be kept uniform by adjusting the K30 value even during the above switching.  
TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK  
filter second-stage output.  
When signals other than the tracking error signal from the RF amplifier are input to the SE input  
pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.  
Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the  
DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2,  
and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to  
M18 can be kept uniform by adjusting the K46 value even during the above switching.  
See "§5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.  
The focus error (FE) and tracking error (TE) can be generated internally.  
When 0, the FE and TE signal input mode results. Input each error signal through the FE and  
TE pins. (default)  
ABEF:  
When 1, the FE and TE signal generation mode results and the FE and TE signals are generated  
internally.  
TLD2 to 0:  
These turn on and off SLD filter correction independently of the TRK filter.  
See $38 (TLC2 to TLC0) and Fig. 5-3.  
Traverse center correction  
TLC2  
TLD2  
TRK filter  
OFF  
SLD filter  
OFF  
0
1
0
ON  
ON  
ON  
OFF  
1
Tracking zero level correction  
TLC1  
TLD1  
TRK filter  
OFF  
SLD filter  
OFF  
0
1
0
ON  
ON  
ON  
OFF  
1
VC level correction  
TLC0  
TLD0  
TRK filter  
OFF  
SLD filter  
OFF  
0
0
1
ON  
ON  
OFF  
1
ON  
: preset, : don't care  
117 –  
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