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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
DRR2 to DRR0: Partially clears the Data RAM values (0 write).  
The following values are cleared when 1 (on) respectively; default is 0  
DRR2: M08, M09, M0A  
DRR1: M00, M01, M02  
DRR0: M00, M01, M02 only when LOCK = low  
Note) Set DRR1 and DRR0 on for 50µs or more.  
ASFG:  
When vibration detection is performed during anti-shock circuit operation, the FCS servo filter  
is forcibly set to gain normal status.  
On when 1; default is 0  
FTQ:  
The slope of the output during focus search is 1/4 the conventional output slope. On when 1;  
default is 0  
SRO1:  
This command is used to continuously externally output various data inside the digital servo  
block which have been specified with the $39 command. (However, D15 (DAC) of $39 must  
be set to 1.)  
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting  
this command to 1.  
SRO1 = 1  
SOCK Output from LMUT pin.  
XOLT Output from WFCK pin.  
SOUT Output from RMUT pin.  
AGHF:  
ASOT:  
This halves the frequency of the internally generated sine wave during AGC.  
The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when 1;  
default is 0.  
Vibration detection when a high signal is output for the anti-shock signal output.  
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