CXD3018Q/R
$3C (preset: $3C 00 80)
D15 D14 D13 D12 D11 D10 D9
COSS COTS CETZ CETF COT2 COT1 MOT2
D8
0
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
BTS1 BTS0 MRC1 MRC0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
COSS
COTS
TZC
1
0
0
—
0
1
STZC
HPTZC
DTZC
: preset, —: don't care
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See §5-13.
CETZ:
CETF:
Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When 0, the TZC signal is generated by using the signal input to the TE pin.
When 1, the TZC signal is generated by using the signal input to the CE pin.
When 0, the signal input to the TE pin is input to the TRK servo filter.
When 1, the signal input to the CE pin is input to the TRK servo filter.
These commands output the TZC signal.
COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from the
COUT pin and the TZC signal is used for auto sequence instead of the COUT signal.
COT1
COT2
COUT pin output
1
0
0
—
1
0
STZC
HPTZC
COUT
: preset, —: don't care
MOT2:
The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from
the MIRR pin and the STZC signal is used for generating the COUT signal instead of the MIRR
signal.
These commands set the MIRR signal generation circuit.
BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is 0.
MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. These bits set that time.
The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R.
BTS1 BTS0 Number of count-up steps per cycle
MRC1 MRC0 Setting time [µs]
0
0
1
1
0
1
0
1
1
2
4
8
0
0
1
1
0
1
0
1
5.669
11.338
22.675
45.351
: preset (when MCK = 128Fs)
– 116 –
ETC [ ETC ]
