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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
$3A (preset: $3A0000)  
D15 D14 D13 D12 D11 D10 D9  
D8  
0
D7  
D6  
D5  
D4  
D3  
D2  
0
D1  
0
D0  
0
0
FBON  
0
0
0
0
FIFZC  
FPS1 FPS0 TPS1 TPS0 SVDA  
FBON:  
FBIAS (focus bias) register operation setting.  
FBON  
Processing  
0
1
FBIAS (focus bias) register addition off.  
FBIAS (focus bias) register addition on.  
FIFZC:  
This selects the FZC slice level setting command.  
When 0, the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default)  
When 1, the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to  
FIFZA0 setting values.  
This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH and  
FZSL setting.  
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.  
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.  
These are effective for increasing the overall gain in order to widen the servo band, etc.  
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,  
6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the  
relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.  
FPS1  
Relative gain  
0dB  
FPS0  
TPS1  
Relative gain  
0dB  
TPS0  
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
+6dB  
+6dB  
+12dB  
+18dB  
+12dB  
+18dB  
: preset  
SVDA:  
This allows the data set by the $39 command to be output through the audio DAC.  
When 0, audio is output. (default)  
When 1, the data set by the $39 command is output.  
113 –  
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