CXD3018Q/R
$39 (preset: $390000)
D15 D14 D13 D12 D11 D10 D9
D8
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
When $3A command SVDA = 0
DAC:
Serial data readout DAC mode setting.
When 0, serial data cannot be read out. (default)
When 1, serial data can be read out.
SD6 to SD0:
These bits select the serial readout data.
D14 D13 D12 D11 D10 D9
D8
Readout data
length
Readout data
SD6 SD5 SD4 SD3 SD2 SD1 SD0
Coefficient RAM address
Data RAM address
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Coefficient RAM data
Data RAM data
RF AVRG register
RFDC input signal
FCS bias register
TRVSC register
DFCT count
8 bits
16 bits
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
: don't care
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
RFDC (Bottom)
RFDC (Peak)
RFDC (Peak – Bottom)
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
1
1
0
0
1
0
1
0
TE input signal
SE input signal
VC input signal
Note) When $3A SVDA is changed, select the readout data again.
The DFCT count counts the number of times the DFCT signal rises while $3994 is set.
Readout outputs the DFCT count at that time.
– 111 –
ETC [ ETC ]
