Datasheet
ZADCS146 / ZADCS147
Figure 11: 16-Clock External Clock Mode Conversion
nCS
1
8
1
8
1
8
1
SCLK
DIN
UNI/ SGL/
BIP DIF
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
S
A2 A1 A0
PD1 PD0
Acquire
(Start)
Conversion
Idle
SSTRB
DOUT
Zero filled
B11 B10 B9 B8 B7 B6 B5
(MSB)
B4
B3 B2 B1 B0
B11 B10
(LSB)
Figure 12: 15-Clock External Clock Mode Conversion
nCS
1
8
15
1
15
1
SCLK
DIN
UNI/ SGL/
BIP DIF
UNI/ SGL/
BIP DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
S
A2 A1 A0
PD1 PD0
Acquire
S
A2
(Start)
Conversion
Conversion
SSTRB
DOUT
Zero filled
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB) (LSB)
B11 B10 B9 B8 B7 B6 B5 B4
Internal Clock Mode
16-Clocks per Conversion
In Internal Clock Mode, the conversion starts at the falling
clock edge of the eighth control bit just as in External
Clock Mode. However, there are no further clock pulses
required at SCLK to complete the conversion. The con-
version clock is generated by an internal oscillator that
runs at approximately 3.2MHz. While the conversion is
running, the SSTRB signal is driven LOW. As soon as the
conversion is complete, SSTRB is switched to HIGH,
signaling that the conversion result can be read out on
the serial interface.
Interleaving of the data read out process and transmis-
sion of a new Control Byte is also supported for External
Clock Mode operation. Figure 11 shows the transmission
timing for conversion runs using 16 clock cycles per run.
In fact, the specified converter sampling rate of 200ksps
will be reached in this mode, provided the clock fre-
quency is set to 3.2MHz.
15-Clocks per Conversion
ZADS146 and ZADCS147 do also support a 15 clock
cycle conversion mode (see Figure 12). This is the fastest
conversion mode possible. Usually micro controllers do
not support this kind of 15 bit serial communication trans-
fers. However, specifically designed digital state ma-
chines implemented in Field Programmable Gate Arrays
(FPGA) or Application Specific Integrated Circuits (ASIC)
may use this operation mode. Applications that utilize the
15 clock cycle conversion mode gain an increase in sam-
pling rate to 213.3ksps keeping the clock frequency un-
changed at 3.2MHz.
To shorten cycle times ZADCS146 and ZADCS147 allow
interleaving of the read out process with the transmission
of a new control byte. Thus it is possible to read the con-
version result and to start a new conversion with just two
consecutive byte transfers, instead of thee bytes that
would have to be send without the interleaving function.
While the IC is performing a conversion in Internal Clock
Mode, the Chip Select signal (nCS) may be tied HIGH
allowing other devices to communicate on the bus. The
output driver at DOUT is switched into a high impedance
state while nCS is HIGH. The conversion time tCONV may
vary in the specified limits depending on the actual VDD
and temperature values.
Digital Timing
In general the clock frequency at SCLK may vary from
0.1MHz to 3.2MHz. Considering all telegram pauses or
other interruptions of a continuous clock at SCLK, each
conversion must be completed within 1.2ms from the
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
14/19
ZMD [ Zentrum Mikroelektronik Dresden AG ]
