Datasheet
ZADCS146 / ZADCS147
Table 6: ZADCS146 / ZADCS147 Timing Characterisitics (VDD = +2.7V to + 5.25V; θOP =θOPmin …θOPmax
)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SCLK Periode
tSCLK
312.50
156.25
ns
ns
SCLK Pulse Width High
tSCLKhigh
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
tSCLKlow
tDinSetup
tDinHold
156.25
30
ns
ns
ns
ns
10
nCS Fall to SCLK Setup
tnCSSetup
30
SCLK Fall to
DOUT & SSTRB Hold
tOutHold
tOutValid
CLoad = 20pF
CLoad = 20pF
10
ns
ns
ns
SCLK Fall to
DOUT & SSTRB Valid
40
60
60
nCS Rise to
DOUT & SSTRB Disable
tOutDisable CLoad = 20pF
10
nCS Fall to
DOUT & SSTRB Enable
tOutEnable CLoad = 20pF
tnCSHigh
ns
ns
nCS Pulse Width High
100
Figure 13: Detailed Timing Diagram
nCS
tSCLKhigh
tnCSSetup
tSCLK
tSCLKlow
tOutValid
SCLK
tDINsetup
tDINhold
DIN
SSTRB
DOUT
tnCSHigh
tOutEnable
tOutDisable
tOutHold
tOutEnable
falling clock edge of the eighth bit in the Control Byte.
Otherwise the signal that was captured during sam-
ple/hold may drop to noticeable affect the conversion
result.
voltage difference of VREF (Full Scale = FS). The first
code transition (0x000 à 0x001) occurs at a voltage
equivalent to ½ LSB, the last (0xFFE à 0xFFF) at
VREF - 1.5 LSB. See also Figure 14 for details.
Further detailed timing information on the digital interface
is provided in Table 6 and Figure 13.
In bipolar mode a two’s complement coding is applied.
Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in
Figure 15.
Output Code Format
ZADCS146 and ZADCS147 both support unipolar and
bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x000 for
an input voltage difference of 0V to 0xFFF for an input
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
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ZMD [ Zentrum Mikroelektronik Dresden AG ]
