Datasheet
ZADCS146 / ZADCS147
2.2 Analog Input
2 DETAILED DESCRIPTION
The analog input to the converter is fully differential. Both
converter input signals IN+ and IN– (see Functional Block
diagram at front page) get sampled during the acquisition
period enabling the converter to be used in fully differen-
tial applications where both signals can vary over time.
2.1 General Operation
The ZADCS146 / ZADCS147 are classic successive
approximation register (SAR) type converters. The archi-
tecture is based on a capacitive charge redistribution
DAC merged with a resistor string DAC building a hybrid
converter with excellent monotonicity and DNL properties.
The Sample & Hold function is inherent to the capacitive
DAC. This avoids additional active components in the
signal path that could distort the input signal or introduce
errors.
The ZADCS146 / ZADCS147 converters do not require
that the negative input signal be kept constant within
± 0.5LSB during the entire conversion as is commonly
required by converters featuring pseudo differential op-
eration only.
The input signals can be applied single ended, refer-
enced to the COM pin, or differential, using four pairs of
the eight input channels. The desired configuration is
selectable for every conversion via the Control-Byte re-
ceived on DIN pin of the digital interface (see further
description below)
Both devices ZADCS146 / ZADCS147 build on the same
converter core and differ only in the availability of an
internal reference voltage generator. ZADCS146 is
equipped with a highly accurate internal 1.25V bandgap
reference which is available at the VREFADJ pin. The
bandgap voltage is further amplified by an internal buffer
amplifier to 2.50V that is available at pin VREF.
ZADCS147 comes without the internal reference and the
internal buffer amplifier. It requires an external reference
supplied at VREF, with the benefit of considerably lower
power consumption.
A block diagram of the input multiplexer is shown in
Figure 4. Table 3 and Table 4 show the relationship of the
Control-Byte bits A2, A1, A0 and SGL/DIF to the configu-
ration of the analog multiplexer.
Both input signals IN+ and IN– are generally allowed to
swing between –0.2V and VDD+0.2V. However, depend-
ing on the selected conversion mode – uniploar or bipo-
lar – certain input voltage relations can limit the output
code range of the converter.
A basic application schematic of ZADC146 is shown in
Figure 2, for ZADC147 in Figure 3. ZADCS146 can also
be operated with an external reference, if VREFADJ is
tied to VDD.
In unipolar mode the voltage at IN+ must exceed the
Table 3: Channel selection in Single Ended Mode
(SGL/DIF = HIGH)
Table 4: Channel selection in Differential Mode
(SGL/DIF = LOW)
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
IN+
IN-
IN-
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN+ IN-
IN+
IN+ IN-
IN+
IN-
IN+ IN-
IN+
IN-
IN+ IN-
IN+
IN-
IN- IN+
IN+
IN-
IN- IN+
IN+
IN-
IN- IN+
IN+ IN-
IN- IN+
Figure 2: Basic application schematic for ZADCS146
Figure 3: Basic application schematic for ZADCS147
+2.7V to 5.25V
Single-ended or differential
+2.7V to 5.25V
Single-ended or differential
analog inputs, 0V … +2.5V
analog inputs, 0V … +2.5V
0.1µF
µC
10µF
0.1µF
µC
10µF
ZADCS146
CH0
ZADCS147
CH0
VDD
SCLK
nCS
VDD
SCLK
nCS
1
2
20
19
18
17
16
15
14
13
12
11
1
2
20
19
18
17
16
15
14
13
12
11
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
nSHDN
SCK
I/O
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
nSHDN
SCK
I/O
3
3
DIN
MOSI
DIN
MOSI
4
4
SSTRB
DOUT
DGND
AGND
VREFADJ
VREF
SSTRB
DOUT
DGND
AGND
n.c.
5
5
MISO
MISO
6
6
7
7
8
8
47nF
9
9
VREF
10
10
≥ 4.7µF
≥ 4.7µF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
10/19
ZMD [ Zentrum Mikroelektronik Dresden AG ]
