Datasheet
ZADCS146 / ZADCS147
This reduces power consumption of the ZADCS146 and
allows the supply of an external reference at VREF.
tACQ
RS
≤
−RSW
9 ×CIN
ZADCS147 does not contain the internal bandgap or the
VREF buffer. An external reference must be supplied all
the time at VREF.
For example, if fSCLK = 3.2MHz, the acquisition time is
tACQ = 781.25ns. Thus the output impedance of the signal
source RS must be less than
The value of the reference voltage at VREF sets the input
range of the converter and the analog voltage weight of
each digital code. The size of the LSB (least significant
bit) is equal to the value of VREF (reference to AGND)
divided by 4096. For example at a reference voltage of
2.500V, the voltage level of a LSB is equal to 610µV.
781.25ns
RS
≤
− 3kΩ = 1.34kΩ
9 × 20pF
If the output impedance of the source is higher than the
calculated maximum RS the acquisition time must be
extended by reducing fSCLK to ensure 12 bit accuracy.
Another option is to add a capacitor of >20 nF to the
individual input. Although this limits the bandwidth of the
input signal because an RC low pass filter is build to-
gether with the source impedance, it may be useful for
certain applications.
It is important to know that certain inherent errors in the
A/D converter, like offset or gain error, will appear to
increase at lower reference voltages while the actual
performance of the device does not change. For instance
a static offset error of 1.22mV is equal to 2 LSB at 2.5V
reference, while it is equivalent to 5.0 LSB for a reference
voltage of 1.0V
The small-signal bandwidth of the input tracking circuitry
is 3.8 MHz. Hence it is possible to digitize high-speed
transient events and periodic signals with frequencies
exceeding the ADC’s sampling rate. This allows the ap-
plication of certain under-sampling techniques like down
conversion of modulated high frequency signals.
Likewise, the uncertainty of the digitized output code will
increase with lower LSB size (lower VREF). Once the
size of an LSB is below the internal noise level, the output
code will start to vary around a mean value for constant
DC input voltages. Such noise can be reduced by averag-
ing consecutive conversions or applying a digital filter.
Be aware that under-sampling techniques still require a
bandwidth limitation of the input signal to less than the
Nyquist frequency of the converter to avoid aliasing ef-
fects. Also, the output impedance of the input source
must be very low to achieve the mentioned small signal
bandwidth in the overall system.
The average current consumption at VREF depends on
the value of VREF and the sampling frequency. Two
effects contribute to the current at VREF, a resistive con-
nection from VREF to AGND and charge currents that
result from the switching and recharging of the capacitor
array (CDAC) during sampling and conversion.
For an external reference of 2.5V the input current at
VREF is approximately 100µA.
2.3 Internal & External Reference
ZADCS146 is equipped with a highly accurate internal
2.5V reference voltage source. The voltage is generated
from a trimmed 1.25V bandgap with an internal buffer that
is set to a gain of 2.00. The bandgap voltage is supplied
at VREFADJ with an output impedance of 20kΩ. An ex-
ternal capacitor of 47nF at VREFADJ is useful to further
decrease noise on the internal reference.
2.4 Digital Interface
ZADCS146 and ZADCS147 are both controlled by a
4-wire serial interface that is compatible to SPI™, QSPI™
and MICROWIRE™ devices without external logic.
Any conversion is started by sending a control byte into
DIN while nCS is low. A typical sequence is shown in
Figure 9.
The VREFADJ pin also provides an opportunity to exter-
nally adjust the bandgap voltage in a limited range (see
Figure 8) as well as the possibility to overdrive the inter-
nal bandgap with an external 1.25V reference.
The control byte defines the input channel(s), unipolar or
bipolar operation and output coding, single-ended or
differential input configuration, external or internal con-
version clock and the kind of power down that is activated
after the completion of a conversion. A detailed descrip-
tion of the control bits can be obtained from Table 5.
Figure 8: Reference Adjust Circuit
VDD = +2.7V … +5.25V
As it can also be seen in Figure 9 the acquisition of the
input signal occurs at the end of the control byte for 2.5
clock cycles. Outside this range, the Track & Hold is in
hold mode.
ZADCS146
The conversion process is started, with the falling clock
edge (SCLK) of the eighth bit in the control byte. It takes
twelve clock cycles to complete the conversion and one
additional cycle to shift out the last bit of the conversion
result. During the remaining three clock cycles the output
is filled with zeros in 24-Clock Conversion Mode.
510kΩ
VREFADJ
47nF
Depending on what clock mode was selected, either the
external SPI clock or an internal clock is used to drive the
successive approximation. Figure 10 shows the Timing
for Internal Clock Mode.
The internal bandgap reference and the VREF buffer can
be shut down completely by setting VREFADJ to VDD.
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
12/19
ZMD [ Zentrum Mikroelektronik Dresden AG ]
