Datasheet
ZADCS146 / ZADCS147
1.3.3 ZADCS147 Specific Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); θOP = θOPmin … θOPmax
)
Parameter
Symbol Conditions
Min
Typ
Max Unit
External Reference at VREF
VREF Input Voltage Range
VDD +
V
1.0
50mV
VREF Input Current
VREF = 2.5V
180
14
215 µA
VREF Input Resistance
11.5
4.7
kΩ
Shutdown VREF Input Current
Capacitive Bypass at VREF
0.1
µA
µF
Power Requirements
Positive Supply Voltage
VDD
2.7
5.25
1.0
4.0
1.3
4.0
V
Operating Mode
Full Power-Down
Operating Mode
Full Power-Down
0.85
0.5
Positive Supply Current
Positive Supply Current
IDD
IDD
VDD = 3.6V
µA
1.00
0.5
VDD
=
µA
5.25V
1.3.4 ZADCS146 / ZADCS147 Digital Pin Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); θOP = θOPmin … θOPmax
)
Parameter
Symbol Conditions
Min
Typ
Max Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
1.9
3.3
V
V
Logic High Level
Logic Low Level
VIH
VIL
0.7
1.4
V
V
V
Hysteresis
VHyst
IIN
0.7
Input Leakage
VIN = 0V or VDD
± 0.1
5
± 1.0 µA
- 5.0 µA
pF
Input Low Leakage @ nSHDN
Input Capacitance
IIN_nSHDN VIN = 0V
CIN
Digital Outptus (DOUT, SSTRB)
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
3.5
5.5
4
8.5
mA
Output High Current
IOH
VOH= VDD – 0.5V
10.8 mA
11.5 mA
15.3 mA
± 1.0 µA
Output Low Current
IOL
VOL= 0.4V
6.4
Three-State Leakage Current
Three-State Output Capacitance
ILeak
nCS = VDD
nCS = VDD
± 0.1
5
COUT
pF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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ZMD [ Zentrum Mikroelektronik Dresden AG ]
