Z8FMC16100 Series Flash MCU
Product Specification
21
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
IRQ1
Reset (Hex)
Page #
57
FC3
FC4
FC5
Interrupt Request 1 Register
00
00
00
XX
00
IRQ1 Enable High Bit Register (IRQ1ENH)
IRQ1 Enable Low Bit Register (IRQ1ENL)
IRQ1ENH
IRQ1ENL
—
60
60
FC9–FCE Reserved
FCF
Interrupt Control Register
IRQCTL
61
GPIO Port A
FD0
FD1
FD2
FD3
Port A Address
PAADDR
PACTL
PAIN
00
00
XX
00
40
41
48
49
Port A Control
Port A Input Data
Port A Output Data
PAOUT
GPIO Port B
FD4
FD5
FD6
FD7
Port B Address
PBADDR
PBCTL
PBIN
00
00
XX
00
40
41
48
49
Port B Control
Port B Input Data
Port B Output Data
PBOUT
GPIO Port C
FD8
FD9
FDA
FDB
Port C Address
PCADDR
PCCTL
PCIN
00
00
XX
00
40
41
48
49
Port C Control
Port C Input Data
Port C Output Data
PCOUT
Reset and Watch-Dog Timer (WDT)
FF0
FF1
FF2
Reset Status and Control Register
RSTSTAT
—
see Table 10
29
Reserved
XX
04
Watch-Dog Timer Reload High Byte Register
(WDTH)
WDTH
66
66
FF3
Watch-Dog Timer Reload Low Byte Register
(WDTL)
WDTL
—
00
FF4–FF5 Reserved
Note: XX = undefined.
XX
PS024604-1005
P R E L I M I N A R Y
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