Z8FMC16100 Series Flash MCU
Product Specification
19
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
Reset (Hex)
Page #
LIN-UART
F40
LIN-UART Transmit Data Register
LIN-UART Receive Data Register
LIN-UART Status 0 Register
LIN-UART Control 0 Register
LIN-UART Control 1
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0MDSTAT
U0ADDR
U0BRH
U0BRL
XX
130
130
131
134
136
133
140
140
141
XX
F41
F42
F43
F44
F45
F46
F47
0000_011Xb
00
00
00
00
FF
FF
XX
LIN-UART Mode Select and Status
LIN-UART Address Compare
LIN-UART Baud Rate High Byte
LIN-UART Baud Rate Low Byte
F48–F5F Reserved
—
2
I C
F50
F51
F52
F53
F54
F55
I2C Data Register
I2CDATA
I2CISTAT
I2CCTL
00
80
00
FF
FF
0X
184
184
186
188
188
189
I2C Interrupt Status Register
I2C Control Register
I2C Baud Rate High Byte Register (I2CBRH)
I2C Baud Rate Low Byte Register (I2CBRL)
I2CBRH
I2CBRL
I2C State Register (I2CSTATE) - Description
when DIAG = 0
I2CSTATE
I2C State Register (I2CSTATE) - Description
when DIAG = 1
I2CSTATE
00
190
F56
F57
I2C Mode Register
I2CMODE
I2CSLVAD
—
00
00
192
193
I2C Slave Address Register
F58–F5F Reserved
XX
SPI
F60
F61
F62
SPI Data Register
SPIDATA
SPICTL
XX
00
01
157
158
159
SPI Control Register
SPI Status Register
SPISTAT
Note: XX = undefined.
PS024604-1005
P R E L I M I N A R Y
ZILOG [ ZILOG, INC. ]
