Z8 Encore!® Motor Control Flash MCUs
Product Specification
18
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
PWMIN
Reset (Hex)
Page #
86
F26
F27
F28
F29
F2A–B
F2C
F2D
F2E
F2F
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F3A
F3B
PWM Input Sample Register
00
00
00
00
XX
00
00
0F
FF
00
00
00
00
00
00
00
00
00
00
00
00
XX
PWM Output Control Register
PWMOUT
PWMFCTL
PWMSHC
—
87
PWM Fault Control Register
85
Current Sense ADC Trigger Control Register
Reserved
87
PWM High Byte Register (PWMH)
PWM Low Byte Register (PWML)
PWM Reload High Byte Register (PWMRH)
PWM Reload Low Byte Register (PWMRL)
PWM 0 High Side Duty Cycle High Byte
PWM 0 High Side Duty Cycle Low Byte
PWM 0 Low Side Duty Cycle High Byte
PWM 0 Low Side Duty Cycle Low Byte
PWM 1 High Side Duty Cycle High Byte
PWM 1 High Side Duty Cycle Low Byte
PWM 1 Low Side Duty Cycle High Byte
PWM 1 Low Side Duty Cycle Low Byte
PWM 2 High Side Duty Cycle High Byte
PWM 2 High Side Duty Cycle Low Byte
PWM 2 Low Side Duty Cycle High Byte
PWM 2 Low Side Duty Cycle Low Byte
PWMH
75
76
76
77
77
78
77
78
77
78
77
78
77
78
77
78
PWML
PWMRH
PWMRL
PWMH0Dh
PWMH0DL
PWML0Dh
PWML0DL
PWMH1DH
PWMH1DL
PWML1DH
PWML1DL
PWMH2DH
PWMH2DL
PWML2DH
PWML2DL
—
F3C–F3F Reserved
Note: XX = undefined.
Register File Address Map
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
