Z8 Encore!® Motor Control Flash MCUs
Product Specification
20
Table 5. Register File Address Map (Continued)
Address
(Hex)
Register Description
Mnemonic
SPIMODE
SPIDST
—
Reset (Hex)
Page #
160
F63
F64
F65
F66
F67
SPI Mode Register
00
00
SPI Diagnostic State Register
Reserved
161
XX
FF
FF
XX
SPI Baud Rate High Byte Register (SPIBRH)
SPI Baud Rate Low Byte Register (SPIBRL)
SPIBRH
SPIBRL
—
162
162
F68–F6F Reserved
Analog-to-Digital Converter (ADC)
F70
F71
F72
F73
F74
F75
F76
ADC Control Register 0
ADCCTL0
ADCRD_H
ADCD_H
ADCD_L
ADCSST
ADCST
ADCCP
—
20
XX
XX
XX
1F
A0
00
203
204
204
205
206
206
207
ADC Raw Data High Byte Register
ADC Data High Byte Register
ADC Data Low Bits Register
Sample Settling Time Register
Sample Time Register
ADC Clock Prescale Register
F77–F85 Reserved
XX
Oscillator Control
F86
F87
Oscillator Control Register
Oscillator Divide Register
OSCCTL
OSCDIV
A0
00
233
234
Trim Control
F88–F8F Reserved
—
XX
Comparator and Op Amp
F90
Comparator and Op Amp Control Register
CMPOPC
—
00
197
F91–FBF Reserved
XX
Interrupt Controller
FC0
FC1
FC2
Interrupt Request 0 Register
IRQ0
00
00
00
55
58
59
IRQ0 Enable High Bit Register (IRQ0ENH)
IRQ0 Enable Low Bit Register (IRQ0ENL)
IRQ0ENH
IRQ0ENL
Note: XX = undefined.
Register File Address Map
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
