Z8FMC16100 Series Flash MCU
Product Specification
323
Bit
Value
(H)
Description
Position
[4]
Fault 1 Restart
Fault1RST
0
1
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
[3
Comparator 0 Interrupt
CMP0INT
0
1
Interrupt on comparator 0 assertion disabled.
Interrupt on comparator 0 assertion enabled.
[2]
Comparator 0 Restart
CMP0RST
0
1
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
[1]
Fault 0 Interrupt
Fault0INT
0
1
Interrupt on Fault0 pin assertion disabled.
Interrupt on Fault0 pin assertion enabled.
[0]
Fault 0 Restart
Fault0RST
0
1
Automatic recovery. PWM resumes control of outputs when all fault sources have
deasserted.
Software controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted and all fault flags are cleared and a PWM reload occurs
Note: This register can only be written when PWENis cleared.
Hex Address: F29
.
Table 169. Current-Sense Trigger Control Register (PWMSHC)
BITS
FIELD
RESET
R/W
7
6
HEN
5
4
LEN
3
2
1
0
CSTPWM2 CSTPWM1 CSTPWM0
CSTPOL
NHEN
NLEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F29H
ADDR
PS024604-1005
P R E L I M I N A R Y
Appendix A—Register Tables
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