Z8FMC16100 Series Flash MCU
Product Specification
327
Bit
Value
(H)
Description
Position
[7]
Duty Cycle Sign
SIGN
0
1
Duty Cycle is a positive two’s complement number.
Duty Cycle is a negative two’s complement number. Output is forced to the off-
state.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
Hex Address: F32
PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SIGN
Reserved
00
DUTYH
0
0_0000
R/W
R/W
R/W
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
Hex Address: F33
PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DUTYL
00H
R/W
F31H, F33H, F35H, F37H, F39H, F3BH
ADDR
PS024604-1005
P R E L I M I N A R Y
Appendix A—Register Tables
ZILOG [ ZILOG, INC. ]
