Z8 Encore!® Motor Control Flash MCUs
Product Specification
320
Hex Address: F25
PWM Fault Status Register (PWMFSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DBGFLAG
RLDFlag Reserved
Reserved
F1FLAG C0FLAG
FFLAG
U
0
U
00
R
U
U
U
R/W1C
R
R/W1C
R/W1C
R/W1C
R/W1C
F25H
ADDR
Bit
Value
(H)
Description
Position
[7]
Reload Flag
RLDFlag
This bit is set and latched when a PWM timer reload occurs. Writing a 1 to this bit
clears the flag.
[6]
0
0
Reserved
Reserved
Always reads 0.
[5]
Debug Flag
DBGFLAG
This bit is set and latched when DEBUG mode is entered. Writing a 1 to this bit
clears the flag.
[4:3]
Reserved
Reserved
Always reads 0.
[2]
Fault1 Flag
F1FLAG
This bit is set and latched when Fault1 is asserted. Writing a 1 to this bit clears
the flag.
[1]
Comparator 0 Flag
C0FLAG
This bit is set and latched when Comparator is asserted. Writing a 1 to this bit
clears the flag.
[0]
Fault Flag
FFLAG
This bit is set and latched when the FAULT0 input is asserted. Writing a 1 to this
bit clears the flag.
Note: For this register, W1C means you must write one to clear the flag.
PS024604-1005
P R E L I M I N A R Y
Appendix A—Register Tables
ZILOG [ ZILOG, INC. ]
