Z8FMC16100 Series Flash MCU
Product Specification
317
Hex Address: F21
PWM Control 1 Register (PWMCTL1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
Pol23
0
2
Pol10
0
1
0
RLFREQ[1:0]
INDEN
Pol45
PRES[1:0]
00
00
0
0
R/W
R/W
R/W
R/W
R/W
R/W
F21H
ADDR
Bit
Value
(H)
Description
Reload Event Frequency
Position
[7:6]
RLFREQ[1:0]
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
00
01
10
11
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
[5]
Independent PWM Mode Enable
INDEN
0
This bit may only be altered when PWEN(PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
1
1
0
1
0
1
0
PWM outputs operate as 6 independent channels.
Invert Output polarity for channel pair PWM2.
Non-inverted polarity for channel pair PWM2.
Invert Output polarity for channel pair PWM1.
Non-inverted polarity for channel pair PWM1.
Invert Output polarity for channel pair PWM0.
Non-inverted polarity for channel pair PWM0.
[4]
Pol2
[3]
Pol1
[2]
Pol0
[1:0]
PWM Prescaler
PRES
The prescaler divides down the PWM input clock (either the system clock or the
PWMIN external input). This field is buffered. Changes to this field take effect at
the next PWM reload event. Reads always return the values from the
temporary holding register.
Divide by 1
00
01
10
11
Divide by 2
Divide by 4
Divide by 8
PS024604-1005
P R E L I M I N A R Y
Appendix A—Register Tables
ZILOG [ ZILOG, INC. ]
