Z8FMC16100 Series Flash MCU
Product Specification
147
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXDpin is
decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 illustrates data recep-
tion. When the infrared endec is enabled, the UART’s RXD signal is internal to the
Z8FMC16100 Series Flash MCU while the IR_RXD signal is received through the RXD
pin.
16-Clock
Period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RxD
Min. 1.6
Pulse
s
UART’s
RxD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8-Clock
Delay
16-Clock
Period
16-Clock
Period
16-Clock
Period
16-Clock
Period
Figure 21. Infrared Data Reception
The system clock frequency must be at least 1.0MHz to ensure proper reception of the
1.6µs minimum-width pulses allowed by the IrDA standard.
Caution:
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected) giving the endec a sampling window of
minus four baud rate clocks to plus eight baud rate clocks around the expected time of an
PS024604-1005
P R E L I M I N A R Y
Receiving IrDA Data
ZILOG [ ZILOG, INC. ]
