Z8FMC16100 Series Flash MCU
Product Specification
109
Bit
Value
(H)
Description
Position
PWM DUAL OUTPUT mode–If enabled, the Timer Output is set=TPOL after
PWM match and set=TPOL after Reload. If enabled the Timer Output
Complement takes on the opposite value of the Timer Output. The PWMD field
in the T0CTL1 register determines an optional added delay on the assertion
(Low to High) transition of both Timer Output and the Timer Output
Complement for deadband generation.
CAPTURE RESTART mode–If the timer is enabled the Timer Output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARATOR COUNTER mode–If the timer is enabled the Timer Output
signal is complemented after timer Reload.
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
TRIGGERED ONE-SHOT mode–If the timer is enabled the Timer Output signal
is complemented after timer Reload.
0 = The timer triggers on a Low to High transition on the input.
1 = The timer triggers on a High to Low transition on the input.
PRES
[5–3]
The timer input clock is divided by 2
, where PRES can be set from 0 to 7.
PRES
The prescaler is reset each time the Timer is disabled. This insures proper clock
division each time the Timer is restarted.
Divide by 1
000
001
010
011
100
101
110
111
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
PS024604-1005
P R E L I M I N A R Y
Timer 0 Control Registers
ZILOG [ ZILOG, INC. ]
