Z8 Encore!® Motor Control Flash MCUs
Product Specification
106
Timer 0 Control Registers
Two Timer 0 control registers determine timer configuration (T0CTL0) and operation
(T0CTL1).
Timer 0 Control 0 Register
The Timer 0 Control 0 (T0CTL0) Register together with the Timer 0 Control 1 (T0CTL1)
Register, determines the timer configuration and operation. See Table 64.
Table 64. Timer 0 Control 0 Register (T0CTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TMODE[3]
TICONFIG
TINSEL
PWMD
INCAP
0
00
0
000
0
R/W
R/W
R/W
R/W
R
F06H
ADDR
Bit
Value
(H)
Description
Timer Mode High Bit
Position
[7]
TMODE[3]
This bit along with the TMODE[2:0] field in the T0CTL1 register determines the
operating mode of the timer. This is the most significant bit of the Timer mode
selection value. See the T0CTL1 register description for additional details.
[6–5]
Timer Interrupt Configuration—This field configures timer interrupt definitions.
These bits affect all modes. The effect per mode is explained below:
TICONFIG
ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM,
TRIGGERED ONE-SHOT, COMPARATOR COUNTER:
0x Timer interrupt occurs on reload.
10 Timer interrupts are disabled.
11 Timer Interrupt occurs on reload.
GATED:
0x Timer interrupt occurs on reload or inactive gate edge.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.
CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only
General-Purpose Timer
P R E L I M I N A R Y
PS024604-1005
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