Z8 Encore!® Motor Control Flash MCUs
Product Specification
88
where
•
•
•
•
the ^ symbol indicates a logical exclusive OR (XOR) function
the & symbol indicates a logical AND function
the | symbol indicates a logical OR function
the ! symbol indicates a logical NOT function
The combinations of polarity, enable, and PWM signals allow the logic to generate a
ADC-trigger under a wide variety of operating conditions. The HEN, LEN, nHEN, and
nLEN bits enable a group in the or logic. The CSTWMx bits allow the level of the PWM
output signals to control the equation. If a CSTPWMx bit is cleared, the value of the asso-
ciated PWMx output will always evaluate to a TRUE condition in the equation. Note that
these bits DO NOT affect the actual PWM outputs.
.
Table 57. Current-Sense Trigger Control Register (PWMSHC)
BITS
FIELD
RESET
R/W
7
6
HEN
5
4
LEN
3
2
1
0
CSTPWM2 CSTPWM1 CSTPWM0
CSTPOL
NHEN
NLEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F29H
ADDR
Bit
Value
(H)
Description
Position
[7]
0
Sample Hold Polarity
CSTPOL
Hold when terms are active
1
0
Hold when terms are not active
High Side Active enable
[6]
HEN
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
Hold when PWM0H, PWM1H, PWM2H are all active
High Side inactive enable
1
[5]
NHEN
0
1
Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation
Hold when are all active
[4]
Low Side Active enable
LEN
0
1
Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation
Hold when PWM0L, PWM1L, PWM2L are all active
Pulse-Width Modulator
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
