Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
124
If the current ADC Analog Input is not the highest numbered input to be converted,
DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
Configuring DMA_ADC for Data Transfer
Follow these steps to configure and enable DMA_ADC:
1. Write the DMA_ADC Address register with the 7 most-significant bits of the Register
File address for data transfers.
2. Write to the DMA_ADC Control register to complete the following:
–
–
–
Enable the DMA_ADC interrupt request, if desired
Select the number of ADC Analog Inputs to convert
Enable the DMA_ADC channel
Caution:
When using the DMA_ADC to perform conversions on multiple ADC in-
puts and the ADC_INfield in the DMA_ADC Control Register is greater
than 000b, the Analog-to-Digital Converter must be configured for Single-
Shot mode.
Continuous mode operation of the ADC can only be used in conjunction
with DMA_ADC if the ADC_INfield in the DMA_ADC Control Register
is reset to 000b to enable conversion on ADC Analog Input 0 only.
DMA Control Register Definitions
DMAx Control Register
The DMAx Control register is used to enable and select the mode of operation for DMAx.
Table 71. DMAx Control Register (DMAxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DEN
DLE
DDIR
IRQEN
WSEL
RSS
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FB0H, FB8H
ADDR
DEN—DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
